1. Field of the Invention
The present invention relates to output drivers and, more particularly, to an output driver with over voltage protection.
2. Description of the Related Art
An output driver is a circuit that sources a substantial current to, or sinks a substantial current from, a capacitive external circuit to drive an output signal onto the external circuit. In addition, output drivers are commonly utilized to provide an interface between a low-voltage digital circuit, such as a circuit that outputs a logic high as a 1.5V signal, and a high-voltage external circuit, such as a circuit that inputs a logic high as a 3.3V signal.
FIG. 1 shows a schematic diagram that illustrates a simple prior-art output driver 100. As shown in FIG. 1, driver 100 includes a PMOS transistor 110 and a NMOS transistor 112. PMOS transistor 110 has a gate, a source connected to an I/O power-supply voltage VDDIO, such as 3.3V, and a drain connected to an external node EXT.
The source and drain of PMOS transistor 110 are formed in an n-type material, such as a well or substrate, which is connected to the I/O power-supply voltage VDDIO. In addition, a channel region is defined between the source arid drain in the n-type material, and a layer of gate oxide is formed over the channel region to isolate the gate from the channel region.
NMOS transistor 112 has a gate, a source connected to ground, and a drain connected to the external node EXT. The source and drain of NMOS transistor 112 are formed in a p-type material, such as a well or substrate, which is connected to ground. In addition, a channel region is defined between the source and drain in the p-type material, and a layer of gate oxide is formed over the channel region to isolate the gate from the channel region.
In operation, when a logic low is output from a digital circuit, the voltage on the gate of PMOS transistor 110 turns off PMOS transistor 110, while the voltage on the gate of NMOS transistor 112 turns on NMOS transistor 112. When NMOS transistor 112 turns on, transistor 112 sinks current from the external node EXT, thereby pulling the voltage on the external node EXT down to ground.
On the other hand, when a logic high is output from the digital circuit, the voltage on the gate of PMOS transistor 110 turns on PMOS transistor 110, while the voltage on the gate of NMOS transistor 112 turns off NMOS transistor 112. When PMOS transistor 110 turns on, transistor 110 sources current to the external node EXT, thereby pulling up the voltage on the external node EXT to the I/O power supply voltage VDDIO, e.g., 3.3V.
One problem with driver 100 is that driver 100 lacks over voltage protection, and thus can not be connected to an external circuit, such as a PCI bus, that carries voltages that are substantially higher than the I/O power supply voltage VDDIO. One reason for this is that if driver 100 were connected to such a circuit, the higher voltages would destroy the oxide layer of transistor 112.
For example, assume that the external node EXT of driver 100 is connected to a PCI bus that experiences a maximum voltage of 5.5V. Further assume that driver 100 is turned off by placing the I/O power supply voltage VDDIO on the gate of PMOS transistor 110, and ground on the gate of NMOS transistor 112. Additionally assume that the I/O power supply voltage VDDIO is equal to 3.3V.
With 3.3V MOS transistors, destructive oxide breakdown typically occurs when the voltage dropped across the layer of gate oxide exceeds approximately 4.2V. In the present example, with ground on the gate of transistor 112 and 5.5V on the drain of transistor 112, 5.5V are dropped across the layer of gate oxide. Since a value of 5.5V is well above the destructive breakdown level of 4.2V, the higher voltage destroys the gate oxide layer.
Another reason that driver 100 can not be connected to an external circuit that sees higher voltages is that transistor 112 sinks a current at these voltages due to punch through. The higher voltage on the drain of transistor 112 increases the drain depletion region to the point where the source and drain depletion regions overlap. This condition, known as punch through, allows current to flow from the drain to the source region.
With 3.3V MOS transistors, punch through typically occurs when the drain-to-source voltage exceeds, approximately 3.7V. In the present example, with ground on the source of transistor 112 and 5.5V on the drain of transistor 112, the drain-to-source voltage is equal to 5.5V. Since a value of 5.5V is well above the punch through level of 3.7V, the higher voltage causes a current to flow.
A further reason that driver 100 can not be connected to an external circuit that sees higher voltages is that transistor 110 turns on at these voltages and injects current into the I/O power supply voltage VDDIO. The higher voltage on the drain of transistor 110 causes the drain to temporarily become the source of transistor 110. As is well known, a PMOS transistor turns on when the gate-to-source voltage is less than the threshold voltage of the transistor, and the source-to-drain voltage is greater than the bias voltage of the transistor.
With 3.3V PMOS transistors, a threshold voltage of xe2x88x920.7V and a bias voltage of +0.2V are common. In the present example, with 3.3V on the source (temporarily functioning as the drain) and gate of transistor 112, and 5.5V on the drain (temporarily functioning as the source) of transistor 112, the gate-to-source voltage is equal to xe2x88x922.2V (3.3xe2x88x925.5), while the source-to-drain voltage is equal to +2.2V (5.5xe2x88x923.3). Since a value of xe2x88x922.2V is well below the threshold voltage of xe2x88x920.7V and a value of +2.2V is well above the bias voltage of +0.2V, PMOS transistor 110 turns on.
In addition to turning on, PMOS transistor 110 also has a forward-biased junction to the well/substrate of transistor 110 that produces a large current flow. As is well known, the source-to-well/substrate junction of a PMOS transistor is forward biased when the voltage on the p+ source region is greater than the voltage on the n-type well/substrate by more than the junction voltage of the transistor. With 3.3V MOS transistors, a junction voltage of +0.7V is common.
In the present example, with 3.3V on the well/substrate of transistor 110 and 5.5V on the drain (temporarily functioning as the source) of transistor 110, the junction voltage is equal to +2.2V (5.5xe2x88x923.3). Since a value of +2.2V is well above the junction voltage of +0.7V, a large current flows across the junction.
FIG. 2 shows a schematic diagram that illustrates a prior-art output driver 200 that includes over voltage protection circuitry. As a result, output driver 200 can be connected to an external circuit, such as a PCI bus, that carries voltages that are substantially higher than the I/O power supply voltage VDDIO.
As shown in FIG. 2, driver 200 includes a PMOS transistor 210, a NMOS transistor 212, and a NMOS transistor 214. PMOS transistor 210 has a gate, a source connected to an I/O power-supply voltage VDDIO, such as 3.3V, and a drain connected to an external node EXT. In addition, the source and drain of transistor 210 are formed in an n-well.
NMOS transistor 212 has a gate connected to the I/O power-supply voltage VDDIO, a source, and a drain connected to the external node EXT. In addition, the source and drain of transistor 212 are formed in a p-type material that is connected to ground. NMOS transistor 214 has a gate, a source connected to ground, and a drain connected to the source of transistor 212. In addition, the source and drain of transistor 214 are formed in the p-type material that is connected to ground.
Driver 200 also includes a PMOS transistor 220, a PMOS transistor 222, and a PMOS transistor 224. PMOS transistor 220 has a gate, a source connected to the I/O power-supply voltage VDDIO, and a drain connected to the n-well. In addition, the source and drain of transistor 220 are formed in the n-well.
PMOS transistor 222 has a gate connected to the I/O power-supply voltage VDDIO, a source connected to the drain of transistor 220, and a drain connected to the external node EXT. In addition, the source and drain of transistor 222 are formed in the n-well. PMOS transistor 224 has a gate connected to the I/O power-supply voltage VDDIO, a source connected to the drain of transistor 220, and a drain connected to the gate of transistor 210. In addition, the source and drain of transistor 224 are formed in the n-well.
Driver 200 further includes a PMOS transistor 230 and an NMOS transistor 232. PMOS transistor 230 has a gate connected to the I/O power-supply voltage VDDIO, a source connected to the external node EXT, and a drain connected to the gate of transistor 220. In addition, the source and drain of transistor 230 are formed in an n-type material that is connected to the external node EXT. NMOS transistor 232 has a gate connected to the I/O power supply-voltage VDDIO, a drain connected to the external node EXT, and a source connected to the gate of transistor 220. In addition, the source and drain of transistor 232 are formed in a p-type material that is connected to ground.
Driver 200 further includes a PMOS transistor 240 and an NMOS transistor 242. PMOS transistor 240 has a gate connected to the gate of transistor 220, a source connected to the gate of transistor 210, and a drain. In addition, the source and drain of transistor 240 are formed in an n-type material that is connected to the gate of transistor 210. NMOS transistor 242 has a gate connected to the I/O power-supply voltage VDDIO, a source connected to the drain of transistor 240, and a drain connected to the gate of transistor 210. In addition, the source and drain of transistor 242 are formed in a p-type material that is connected to ground.
In operation, transistor 212 is always turned on since the gate of transistor 212 is connected to the I/O power-supply voltage VDDIO. In addition, when driver 200 outputs data, such as to a PCI bus, transistor 242 is always turned on. As a result, when the signal output from a digital circuit is a logic low, the voltage on the gate of PMOS transistor 210 turns off PMOS transistor 210, while the voltage on the gate of NMOS transistor 214 turns on NMOS transistor 214. When NMOS transistor 214 turns on, transistor 214 sinks current from the external node EXT, thereby pulling the voltage on the external node EXT down to ground.
On the other hand, when the signal output from the digital circuit is a logic high, the voltage on the gate of PMOS transistor 210 turns on PMOS transistor 210, while the voltage on the gate of NMOS transistor 212 turns off NMOS transistor 212. When PMOS transistor 210 turns on, transistor 210 sources current to the external node EXT, thereby pulling up the voltage on the external node EXT to the I/O power supply voltage VDDIO, e.g., 3.3V.
When driver 200 is not outputting data and the voltage on the external node EXT rises to a voltage greater than the I/O power-supply voltage VDDIO, such as to 5.5V, transistor 212 protects transistor 214 from both destructive oxide breakdown and punch through.
Since the gate of transistor 212 is connected to the I/O power supply voltage VDDIO, the voltage on the source of transistor 212 and the drain of transistor 214 is limited to the I/O power supply voltage VDDIO less the threshold voltage VTH of transistor 212. Thus, with an I/O power supply voltage VDDIO equal to 3.3V and a threshold voltage equal to +0.7V, the voltage on the drain of transistor 214 is limited to approximately +2.6V which is less than the destructive oxide breakdown level of 4.2V and the punch through level of 3.7V. As a result, transistor 214 is protected from the over voltage condition.
In addition, when the voltage on the external node EXT rises to 5.5V, transistor 210 is protected from turning on and from forward biasing the junction. When 5.5V are on the external node EXT, transistor 222 turns on. When transistor 222 turns on, the n-well charges up to the voltage on the external node EXT, e.g., 5.5V.
As a result, the voltage on the drain (functioning as the source) of transistor 210 and the voltage on the n-well of transistor 210 are both equal to 5.5V. Thus, the voltage across the junction is equal to zero which, in turn, is less than the junction voltage of 0.7V, thereby insuring that the junction is not forward biased.
Further, since the source of transistor 224 is connected to the n-well and the gate of transistor 224 is connected to the I/O power supply voltage VDDIO, transistor 224 turns on when the voltage on the n-well rises to 5.5V. As a result, the voltage on the gate of transistor 210 rises to approximately 5.5V. Since 5.5V are now on both the gate and drain (functioning as the source) of transistor 210, transistor 210 remains off.
Thus, since transistors 210 and 214 are both protected from an over voltage condition, driver 200 can be connected to an external circuit, such as a PCI bus, that carries voltages that are substantially higher than the I/O power supply voltage VDDIO.
In addition, transistors 230 and 232 pass the voltage on the external node EXT to the gates of transistor 220 and 240. Thus, when 5.5V are on the external node EXT, transistor 220 turns off. Further, since 5.5V is on both the gate and source of transistor 240, transistor 240 is also turned off.
Additionally, the voltage on the source of transistor 242 is limited to a threshold voltage drop less than the I/O power supply voltage VDDIO. As a result, transistors 240 and 242 protect the circuits that drive transistor 210 when 5.5V are on the external node EXT. When driver 200 again outputs data, transistor 220 turns on and returns the voltage on the n-well to the I/O power supply voltage VDDIO.
FIG. 3 shows a schematic diagram that illustrates another prior-art output driver 300 that includes over voltage protection circuitry. As shown in FIG. 3, driver 300 includes a PMOS transistor 310, a NMOS transistor 312, and a NMOS transistor 314. PMOS transistor 310 has a gate, a source connected to an I/O power-supply voltage VDDIO, such as 3.3V, and a drain connected to an external node EXT. In addition, the source and drain of transistor 310 are formed in an n-well 316.
NMOS transistor 312 has a gate connected to the I/O power-supply voltage VDDIO, a source, and a drain connected to the external node EXT. In addition, the source and drain of transistor 312 are formed in a p-type material that is connected to ground. NMOS transistor 314 has a gate, a source connected to ground, and a drain connected to the source of transistor 312. In addition, the source and drain of transistor 314 are formed in the p-type material that is connected to ground.
Driver 300 also includes a PMOS transistor 320, a PMOS transistor 322, and a resistive element R1. PMOS transistor 320 has a gate, a source connected to the I/O power-supply voltage VDDIO, and a drain. In addition, the source and drain of transistor 320 are formed in n-well 316.
PMOS transistor 322 has a gate connected to the I/O power-supply voltage VDDIO, a drain connected to the gate of transistor 320, and a source connected to the drain of transistor 320. In addition, the source and drain of transistor 322 are formed in n-well 316. Resistive element R1, which can be implemented with a number of NMOS transistors in series, is connected between the gate of transistor 320 and ground.
Driver 300 further includes a PMOS transistor 330, a PMOS transistor 332 and a resistor R2. PMOS transistor 330 has a gate connected to the I/O power-supply voltage VDDIO, a source connected to the drain of transistor 320, and a drain connected to the gate of transistor 310. In addition, the source and drain of transistor 330 are formed in n-well 316. PMOS transistor 332 has a gate connected to the I/O power-supply voltage VDDIO, a source connected to the drain of transistor 320, and a drain connected to n-well 316. In addition, the source and drain of transistor 332 are formed in n-well 316. Resistor R2, in turn, is connected between the sources of transistors 330 and 332 and the external node EXT.
Driver 300 further includes a PMOS transistor 334, a PMOS transistor 336 and a NMOS transistor 338. PMOS transistor 334 has a gate, a source connected to the I/O power-supply voltage VDDIO, and a drain connected to n-well 316. In addition, the source and drain of transistor 334 are formed in n-well 316.
PMOS transistor 336 has a gate connected to the I/O power-supply voltage VDDIO, a source connected to the drain of transistor 320, and a drain connected to the gate of transistor 334. In addition, the source and drain of transistor 336 are formed in n-well 316. NMOS transistor 338 has a gate connected to the I/O power-supply voltage VDDIO, a drain connected to the drain of transistor 320, and a source connected to the gate of transistor 334. In addition, the source and drain of transistor 338 are formed in a p-type material connected to ground.
Driver 300 further includes a PMOS transistor 340 and an NMOS transistor 342. PMOS transistor 340 has a gate connected to the gate of transistor 320, a source connected to the gate of transistor 310, and a drain. In addition, the source and drain of transistor 340 are formed in an n-type material that is connected to the gate of transistor 310. NMOS transistor 342 has a gate connected to the I/O power-supply voltage VDDIO, a source connected to the drain of transistor 340, and a drain connected to the gate of transistor 310. In addition, the source and drain of transistor 342 are formed in a p-type material that is connected to ground.
In operation, transistor 312 is always turned on since the gate of transistor 312 is connected to the I/O power-supply voltage VDDIO. In addition, when driver 300 outputs data, transistor 342 is always turned on. As a result, when the signal output from a digital circuit is a logic low, the voltage on the gate of PMOS transistor 310 turns off PMOS transistor 310, while the voltage on the gate of NMOS transistor 314 turns on NMOS transistor 314. When NMOS transistor 314 turns on, transistor 314 sinks current from the external node EXT, thereby pulling the voltage on the external node EXT down to ground.
On the other hand, when the signal output from the digital circuit is a logic high, the voltage on the gate of PMOS transistor 310 turns on PMOS transistor 310, while the voltage on the gate of NMOS transistor 312 turns off NMOS transistor 312. When PMOS transistor 310 turns on, transistor 310 sources current to the external node EXT, thereby pulling up the voltage on the external node EXT to the I/O power supply voltage VDDIO, e.g., 3.3V.
When driver 300 is not outputting data and the voltage on the external node EXT rises to a voltage greater than the I/O power-supply voltage VDDIO, such as to 5.5V, transistor 312 protects transistor 314 from both destructive oxide breakdown and punch through in the same manner that transistor 212 protects transistor 214.
In addition, when the voltage on the external node EXT rises to 5.5V, transistor 310 is protected from turning on and from forward biasing the junction. Resistor R2 passes the voltage on the external node EXT to the sources of transistors 322, 330, 332, and 336, and the drains of transistors 320 and 338.
The 5.5V passed to the sources of transistors 330 and 332 turn on these transistors. When transistor 330 turns on, the 5.5V on the source are passed to the gate of transistor 310. Since 5.5V is now on the gate and drain (functioning as the source) of transistor 310, transistor 310 remains off.
When transistor 332 turns on, n-well 316 charges up to 5.5V. As a result, the voltage on the drain (functioning as the source) of transistor 310 and the voltage on n-well 316 of transistor 310 are both equal to 5.5V. Thus, the voltage across the junction is equal to zero which, in turn, is less than the junction voltage of 0.7V, thereby insuring that the junction is not forward biased.
In addition, when the voltage on the external node EXT rises to 5.5V, transistor 322 turns on. When transistor 322 turns on, the 5.5V are passed to the gates of transistors 320 and 340, thereby turning off these transistors. Further, the 5.5V on the sources of transistors 330 and 332 turn on transistor 336 which, in turn, turns off transistors 334 and 338.
When driver 300 again outputs data, transistor 322 turns off. When transistor 322 turns off, the voltage on the gate of transistor 320 is pulled low via resistive element R1, thereby turning on transistor 320. As a result, the I/O power-supply voltage VDDIO is placed on the source of transistor 336, which turns off transistor 336, and on the drain of transistor 338.
Transistor 338 then turns on which, in turn, places the I/O power-supply voltage VDDIO on the gate of transistor 334. Since 5.5V is initially on n-well 316, transistors 332 and 334 turn on until the voltage on n-well 316 has fallen to approximately the I/O power supply voltage VDDIO.
Although output drivers 200 and 300 provide over voltage protection, there is a need for alternate circuits for providing over voltage protection.
The present invention provides an output driver with an over voltage protection circuit that is connected between an internal node and an external node. The over voltage protection circuit includes a pass/isolation element that is connected to the internal and external nodes. The pass/isolation element has a first control node. The pass/isolation element passes a voltage on the internal node to the external node when a signal on the first control node is in a first logic state. The pass/isolation element isolates the internal node from the external node when the signal on the first control node is in a second logic state.
The over voltage protection circuit also includes a first control element that is connected to the external node, the first control node, a ground node, and a power supply node. The control element places the signal in the first logic state when a voltage on the external node is less than the sum of a supply voltage on the power supply node and a predefined voltage. The control element places the signal in the second logic state when a voltage on the external node is greater than the sum of the supply voltage and the predefined voltage.
The over voltage protection circuit can also include a voltage-setting element that is connected to the internal node and the power supply node. The voltage-setting element has a second control node. The voltage-setting element passes the supply voltage to the internal node when a signal on the second control node of the voltage-setting element is in a first logic state. The voltage-setting element isolates the supply voltage from the internal node when the signal on the second control node is in a second logic state.
The over voltage protection circuit can further include a second control element that is connected to the first control node, the second control node, a ground node, and the power supply node. The second control element places the signal on the second control node in the first logic state when a voltage on the external node is greater than the sum of the supply voltage and a predefined voltage. The second control element places the signal on the second control node in the second state when a voltage on the external node is less than the sum of the supply voltage and the predefined voltage.
The over voltage protection circuit can alternately include a voltage-setting element that is connected to the internal node, the external node, and the power supply node. The voltage-setting element sources a current to the internal node.
The driver of the present invention can also include a first driver element that is connected to the internal node. The first driver element has a third control node, and sources current to the internal node when a signal on the third control node is in a first logic state, and turns off when the signal on the third control node is in a second logic state.
The driver of the present invention can further include a second driver element that is connected to the internal node. The second driver element has a fourth control node, and sinks current from the internal node when a signal on the fourth control node is in a second logic state, and turns off when the signal on the second control node is in a first logic state.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.